Superconducting PCB technologies & materials
Compare aluminum and tin-based superconducting traces, see which vias can superconduct, and choose a substrate that behaves at cryogenic temperatures.
Quantum PCB
Five technologies
Choosing a superconducting trace
If you will use aluminum wire or wedge bonding, choose aluminum traces. If you won't, a tin-based finish on a standard copper board may be all you need.
Preliminary notes. Aluminum-trace technology is still developing, so values on this page may change. Confirm the details for your design with our engineering team.
| Technology | Tc (K) | Wire bonding | Soldering | Inner-layer traces |
|---|---|---|---|---|
| Aluminum traces | 0.4–1.1 ¹ | Good | Special flux and technique | Good |
| Immersion tin | 3 | OK for fewer than 20 bonds | Easy | Not superconducting ² |
| Plated tin | 3.3–3.4 | Difficult | Easy | OK on FR4 |
| HASL | > 7 | Not good | Easy, but melts nearby | Not suitable ³ |
| Plated lead-tin | > 7 | Not good | Easy, but melts nearby | Not suitable ³ |
- Depends on the aluminum used: pure aluminum 1.1 K, C-foil 1 K, CAC-foil 0.65 K, Q-Foil 0.4 K.
- Heat from lamination will probably dissolve the pure tin layer into the copper, and the trace will no longer superconduct.
- Heat from lamination melts HASL and lead-tin, and it spreads.
| Technology | Superconducting vias? | Cost | Fabrication |
|---|---|---|---|
| Aluminum foil traces | No. Copper vias possible, but not superconducting | Higher than copper PCBs | Enigma-specific process |
| Electroplated aluminum traces | Yes, but only between two layers | Higher than copper PCBs, plus a batch charge | Enigma-specific process |
| Immersion tin | Outer layers only | Similar to copper PCBs | Special immersion tin solution |
| Plated tin | Inner layers possible | Similar to copper PCBs | Standard copper PCB |
| HASL | Outer layers only | Similar to copper PCBs | Standard copper PCB |
| Plated lead-tin | Outer layers only | Similar to copper PCBs | Standard copper PCB; rare because of RoHS |
Immersion tin caution: many immersion tin finishes don't deposit enough tin to superconduct. Lead-tin is getting harder to source.
Aluminum options
Foil or electroplated aluminum
All aluminum options are wire-bondable but difficult to solder.
| Aluminum | Tc (K) | Vias | Copper seed layer | Substrates |
|---|---|---|---|---|
| Electroplated aluminum | 1.1 | Superconducting ³ | Required ¹ ² | Pre-qualified substrates only ⁴ |
| CAC-foil (30 µm) | 0.65 | Copper only | Preferred (5 µm) | Any except TMM10i |
| Q-Foil (14–17 µm) | 0.4 | Copper only | None | Any except TMM10i |
| C-foil (25 µm) | 1 | Copper only | None | FR4 preferred ⁵ |
| C-foil (50 µm) | 1 | Copper only | None | FR4 preferred ⁵ |
- Aluminum will not electroplate directly onto the substrate, so a copper seed layer is needed.
- Copper seed and aluminum can be plated to any reasonable thickness.
- Between two layers only: outer to outer, or inner to inner (buried). See below.
- See substrate compatibility below.
- C-foil adheres poorly to most substrates but is OK on FR4. TMM10i has no suitable prepreg, so foils can't be used with it.
Foil method
Aluminum foil is laminated like copper foil. Vias are plated copper, not superconducting. When a hole is drilled, the exposed aluminum is first plated with copper before the standard plated-through-hole process.
- Vias joining ground planes are straightforward (not superconducting)
- In multilayers, every inner layer must connect electrically to the outside so it can be plated
- Vias to buried, isolated traces are harder; we are investigating microvias
Electroplated (E-plate) method
The board is built as a copper PCB, including plated-through holes, and aluminum is then electroplated onto the copper. This allows superconducting vias in some cases.
- Aluminum always needs a copper seed layer. It can't be plated onto bare substrate or onto aluminum.
- So a via can be fully superconducting to two layers at most
- A trace can step from aluminum-on-copper to copper-on-aluminum-on-copper, but not back to bare base copper
- So an aluminum trace can't transition into a superconducting tin trace
- Adds a batch charge and lead time; we confirm both with your quote
Superconducting vias
Which connections can superconduct
Single core, layer 1 to layer 2. Fully superconducting.
Through a multilayer, layer 1 to layer 4. Superconducting between the outer layers. Inner layers 2 and 3 connect through base copper, so not superconducting to them.
Buried via, layer 2 to layer 3. Superconducting between the two inner layers. Resin from the prepreg flows into the hole during lamination.
Under development: depth-controlled drilled vias, drilled at the same stage as the through via, then flash plated and electroplated with aluminum. These are not a superconducting connection from layer 1 to layer 2.
RF structures
Surface and buried transmission lines
Surface RF: microstrip and coplanar waveguide
- Single-core microstrip and coplanar waveguide with backside ground are relatively easy to build with a fully superconducting signal path
- Vias joining the ground planes can easily be made superconducting
- Copper patches can go anywhere you need to solder
Buried RF: stripline and edge-coupled stripline
- Build as core + prepreg + core, or foil + prepreg + core + prepreg + foil (four metal layers); a three-metal-layer stack-up isn't practical
- Reaching inner layers with a superconducting via is harder with aluminum; ending traces in bond pads or solderable vias is difficult
- Laser ablation to expose the inner layer is simple and effective, though more expensive, and makes it easier to hold 50 Ω
Substrates
Substrate compatibility
All of these substrates are compatible with cryogenic temperatures.
| Technology | Substrates |
|---|---|
| Electroplated aluminum | Arlon EMD 528K, Rogers TMM10i, Rogers 4450F + Rogers 4350, polyimide. Not FR4. ¹ |
| CAC-foil, Q-Foil | Any substrate except TMM10i ² |
| C-foil (25 or 50 µm) | FR4 preferred, not TMM10i ² ³ |
| Immersion tin, plated tin, HASL, plated lead-tin | Any substrate |
- Substrates must be pre-qualified for the aluminum electroplating process. Only these four are.
- TMM10i has no suitable prepreg, so aluminum foils can't be used with it.
- C-foil adheres poorly to most substrates but is OK on FR4.
Dielectric constant at cryogenic temperatures
Substrates whose Dk barely changes when cold let you check controlled impedance at room temperature, which makes layout iterations faster.
| Substrate | Datasheet Dk | Measured Dk ¹ | Change at 4 K | Datasheet Df |
|---|---|---|---|---|
| Rogers 4450F + Rogers 4350 | 3.5 | – | Dk down 2.5% | 0.0035 |
| Isola P96 polyimide | 3.76 | – | – | 0.017 |
| Arlon EMD 528K + prepreg | 3.2–3.5 | 4.25 | Dk down 2.75% | 0.0036 |
| Rogers TMM10i | 9.8 | 11.17 | Dk up 0.5% | 0.002 |
- Measured with a microstrip resonator; method below.
How to measure Dk at cryogenic temperatures
- Build a microstrip transmission line and confirm 50 Ω with a time-domain reflectometer (TDR).
- Cut the line in two places to make a linear resonator, and measure the resonator's length carefully; it is the key number. Make sure the cuts fully sever the line. The gap width sets the coupling, so adjust it for the sharpest resonance.
- Measure the resonance with a network analyzer (transmission, S21), at room temperature and at cryogenic temperature. A frequency shift means a Dk shift.
- Calculate Dk with the Rogers Corporation Ring Resonator software. Because you built a linear resonator rather than a ring, set the mean ring radius to the resonator length ÷ π, the ring conductor width to your microstrip width, and use your substrate thickness.
- Adjust Dk in the calculator until its node frequency matches your measured peak. That Dk is your measured Dk at that frequency.
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