Capabilities

Specs & design guidelines

Manufacturing capabilities and layout guidance to help your boards build faster, with better yield and lower cost.

Manufacturing capabilities

These capabilities help designers understand how configuration settings affect manufacturability at the layout stage. If you need capabilities beyond those listed, contact us to discuss your requirements.

CapabilityStandardAdvanced
Builds
1 layer, 2 layer0.032" – 0.125" [0.80 – 3.20 mm]0.008" – 0.031" [0.20 – 0.75 mm]
4 layer – 24 layerMin. core thickness 0.005" [0.13 mm]Min. core thickness 0.003" [0.076 mm]
HybridYes
Controlled impedanceYes
Laminate materials
FR4Ventec, Nan YaIsola 370HR, Megtron 6, FR408-HR
High frequencyRogers, Arlon, Isola
Thermal managementBergquist, Ventec, Laird
High temperatureIsola P95 Polyimide, 1 & 2 layers onlyIsola P95 Polyimide multilayer
Design parameters
Smallest drill diameter0.0098" [0.25 mm]0.0059" [0.15 mm]
Smallest via pad diameter0.020" [0.50 mm]0.014" [0.36 mm]
Plated hole to copper0.010" [0.25 mm]0.007" [0.18 mm]
Hole wall plating (min. avg.)0.0008" [0.02 mm] IPC Class 20.001" [0.025 mm] IPC Class 3
Aspect ratio10:113:1
Blind & buried via processingN/AAvailable
Heavy Cu plating (min. avg.)N/AAvailable
Blind microvia Cu fillN/ATBA
Non-conductive viafillYes
Conductive viafillYes
Solder mask swell (annular)0.003" [0.075 mm]0.001" [0.025 mm]
Solder mask dam0.003" [0.075 mm], 0.004" for black0.002" [0.050 mm]
Legend line width0.005" [0.13 mm]0.003" [0.075 mm]
Legend to copper clearance0.005" [0.13 mm]0.005" [0.13 mm]
Cu to board edge – V-score0.020" [0.50 mm]0.015" [0.38 mm]
Cu to board edge – routed0.010" [0.25 mm]0.005" [0.13 mm]
Cu to board edge – inner0.015" [0.38 mm]0.015" [0.38 mm]
Trace/space – ¼ oz CuN/A0.003" [0.075 mm], outer foil only
Trace/space – ⅜ oz CuN/A0.003" [0.075 mm], outer foil only
Trace/space – ½ oz Cu0.005" [0.13 mm]0.004" [0.10 mm]
Trace/space – 1 oz Cu0.007" [0.18 mm]0.005" [0.13 mm]
Trace/space – 2 oz Cu0.010" [0.25 mm]0.008" [0.20 mm]
Trace/space – 3 oz CuN/A0.014" [0.35 mm]
Solder mask
Liquid photo-imageableGreen, Blue, Red, Black, Transparent, Purple, White
Direct imagingYes, all solder mask direct imaged
Via plug (IPC-4761, Type IV)Yes
Filled (IPC-4761, Type VII)Yes
Legend
InkjetWhite
Liquid photo-imageableWhite, Black, YellowBlue, Red, Green
Final finish
ENIGYes
Immersion silverYes
Flash gold (full body)Yes
HASL (tin/lead)Yes
Hard goldYes
Carbon pasteYes
OSPYes
Soft goldYes (outsourced)
ENEPIGYes (outsourced)
DI goldYes (outsourced)
Immersion tinYes (outsourced)
CNC machining
Router bit diameter0.0945" [2.40 mm]0.0157" [0.40 mm] – 0.125" [3.175 mm]
Countersink82°, 90°, 100°, 110°
Back drillYes
MillingYes
CounterboreYes
V-scoreYes
Jump scoreYes
Edge bevelYesRecessed
Edge platingYes
Castellated edgesMin. dia. 0.020" [0.50 mm]
Capability sheet rev. R13, updated October 2026 Quality: ISO 9001:2015 · AS9100D · UL approved, File E64339 Download as PDF (2 pages)
Advanced PCB materials

More than standard FR4

Next-generation electronics need more than standard FR4. We build with materials engineered for performance, reliability and harsh environments.

Low-loss laminates for RF and AI systems

  • Low dielectric loss for high-frequency signal integrity
  • Stable electrical performance at mmWave frequencies and high data rates
  • Faster, more efficient RF and AI hardware

High-Tg materials for thermal stability

  • High glass transition temperature (Tg ≥ 170 °C)
  • Resists heat and dimensional change during assembly and operation
  • Improved reliability in high-temperature environments

Aluminum and cryogenic-compatible materials

  • Aluminum PCBs for thermal management and lightweight designs
  • Cryogenic-compatible materials that keep performing at ultra-low temperatures
  • Built for quantum computing and quantum sensing hardware
Quantum PCB

Have a material requirement that isn't listed in our capability sheets? Ask us; we'll tell you what we can build.

Ask about materials
Manufacturing guidelines

Design tips for better yield and lower cost

Select a topic to expand it.

Fabrication drawing / manufacturing instructions

Ideally supplied as a single design layer or as an Adobe PDF, this drawing should detail all the fabrication requirements for the part along with fully dimensioned mechanical details, including a reference drill drawing. Details not to overlook include:

  • Specify maximum allowable radius for inside corners (r0.050" preferred).
  • Specify base copper thickness for all circuit layers.
  • Identify holes as plated or non-plated.
  • Sort hole sizes in ascending order.

You need to tell us:

  • Board dimensions and tolerances
  • Finished thickness* / multilayer stack-up detail
  • Dielectric specifications (if any)
  • Plating finish
  • Solder mask colour
  • Legend colour
  • Controlled impedance (if any)

* Measured over exposed conductors.

Board outline / routing / scoring profile

One of the design layers should include a board outline. Like circuitry artwork, board profiles should be accurately drawn, without dimensions. Dimensioned drawings should be supplied separately. All lines should be drawn with a single tool, aperture, or pen, with an assumed thickness of zero. Only the centres of drawing lines will be used as definitions for machined board edges. Each line drawn will represent an edge of the finished PCB.

  • It is useful to provide a reference dimension from a non-plated hole to a board edge.
  • Crop marks or layer registration marks are not required on each data layer; however, care should be taken to output all layers with the same datum point.
Tool changes

Optimizing hole diameters (minimizing the number of hole sizes) within your design, and ideally within your CAD library, can help to reduce PCB fabrication cost.

Trace / space / copper weight

Unless otherwise dictated by current handling requirements, Enigma recommends the use of ½ oz base Cu. Compared to 1 oz base Cu, ½ oz Cu provides the following benefits:

  • A reduction in etch loss means that it is easier to resolve the design width of traces and component lands on the finished part. This is particularly advantageous on controlled impedance designs or on designs using fine-pitch devices.
  • A reduced environmental impact.

With standard processing, outer layer conductors as well as those on layers with blind or buried vias receive additional electroplated copper during the metallization of the layer-to-layer interconnects (via holes). Please refer to Enigma's prepared stack-up detail for estimated finished Cu thickness.

Plane layers
  • Wherever possible, create flash (negative) planes instead of drawn (copper pour) planes, as the reduced data size improves processing time.
  • Drawn planes should be filled using the largest line width possible to produce the required fill resolution. Filling drawn planes in a single direction also reduces the size of the data set.
  • If hatched fill is used, orthogonal hatch (not diagonal) is preferred.
  • Voids in hatched planes should not be smaller than 0.015" × 0.015".
Arcs and circles

Arcs and circles should be represented in the CAD database and the resulting output file as true circular entities. Many CAD systems create or output arcs and circles as hundreds of short line segments, which are problematic for CAM systems. Apart from dramatically increasing the data size of a file, segmented arcs can reduce already critical feature-to-feature spacing.

Solder mask opening / solder dams

When creating solder mask openings, consistency is important. If possible, avoid different solder mask annular ring clearances. We recommend that a solder mask pad be equal in size to the copper pad (except fiducials). During tooling, Enigma will increase the solder mask clearance to the required size.

If solder dams (the distance between edges of solder mask openings for adjacent pads) are required, the minimum solder dam width is 0.003". Allow at least 0.008" between the edges of adjacent copper pads to account for solder mask clearances when solder dams are required.

Note: solder dams cannot be achieved on SMT devices of ≤ 0.0157" pitch.

Ident / component legend / screen print
  • For improved clarity, use 0.005" lines for all screen-printed text and graphics.
  • Keep all screen print features at least 0.005" away from solder pads.

Note: all features within 0.005" of solder pads will be clipped away to achieve IPC specifications.

Gerber & drill output
  • To reduce rounding errors, use a minimum of 4 decimal places for outputs in imperial units and 5 decimal places for metric.
  • Use the same output precision for Gerber and drill outputs.
  • Create library footprints with high precision if the software has a separate setting for the library.
  • Output all layers as viewed from the top (primary) side using the same origin.
  • Do not set data output to mirror any layers.
  • Review all files in a standalone Gerber viewer before sending them to a manufacturer.
  • ODB++ is also accepted.
Controlled impedance

The following is required to validate controlled impedance requirements before fabrication:

  • Signal layer
  • Reference plane layer(s)
  • Impedance line width (preferably isolated on the layer by a unique line width)
  • The desired impedance value with tolerance
  • A suggested board stack-up

The fabricator must be given the latitude to suggest adjustments to all of the above to achieve the desired nominal impedance value.

Gold fingers & selective hard gold
  • A plating bar connecting gold fingers together is not required.
  • Maintain a minimum 0.030" clearance between the edge of a gold finger or selective hard gold feature and any plated through-hole feature.
In closing: bigger is better

While your design might well meet your fabricator's minimum capabilities for conductor size and spacing, gains in production yield, and so a lower part cost over the life of the product, can be realized by running a clean-up pass during the design stage. The extra effort to increase the parameters where possible, by even just 1 mil, is good design practice and pays dividends in the long run.

Please contact us for clarification on any design issue.

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