Specs & design guidelines
Manufacturing capabilities and layout guidance to help your boards build faster, with better yield and lower cost.
Manufacturing capabilities and layout guidance to help your boards build faster, with better yield and lower cost.
These capabilities help designers understand how configuration settings affect manufacturability at the layout stage. If you need capabilities beyond those listed, contact us to discuss your requirements.
| Capability | Standard | Advanced |
|---|---|---|
| Builds | ||
| 1 layer, 2 layer | 0.032" – 0.125" [0.80 – 3.20 mm] | 0.008" – 0.031" [0.20 – 0.75 mm] |
| 4 layer – 24 layer | Min. core thickness 0.005" [0.13 mm] | Min. core thickness 0.003" [0.076 mm] |
| Hybrid | Yes | |
| Controlled impedance | Yes | |
| Laminate materials | ||
| FR4 | Ventec, Nan Ya | Isola 370HR, Megtron 6, FR408-HR |
| High frequency | Rogers, Arlon, Isola | |
| Thermal management | Bergquist, Ventec, Laird | |
| High temperature | Isola P95 Polyimide, 1 & 2 layers only | Isola P95 Polyimide multilayer |
| Design parameters | ||
| Smallest drill diameter | 0.0098" [0.25 mm] | 0.0059" [0.15 mm] |
| Smallest via pad diameter | 0.020" [0.50 mm] | 0.014" [0.36 mm] |
| Plated hole to copper | 0.010" [0.25 mm] | 0.007" [0.18 mm] |
| Hole wall plating (min. avg.) | 0.0008" [0.02 mm] IPC Class 2 | 0.001" [0.025 mm] IPC Class 3 |
| Aspect ratio | 10:1 | 13:1 |
| Blind & buried via processing | N/A | Available |
| Heavy Cu plating (min. avg.) | N/A | Available |
| Blind microvia Cu fill | N/A | TBA |
| Non-conductive viafill | Yes | |
| Conductive viafill | Yes | |
| Solder mask swell (annular) | 0.003" [0.075 mm] | 0.001" [0.025 mm] |
| Solder mask dam | 0.003" [0.075 mm], 0.004" for black | 0.002" [0.050 mm] |
| Legend line width | 0.005" [0.13 mm] | 0.003" [0.075 mm] |
| Legend to copper clearance | 0.005" [0.13 mm] | 0.005" [0.13 mm] |
| Cu to board edge – V-score | 0.020" [0.50 mm] | 0.015" [0.38 mm] |
| Cu to board edge – routed | 0.010" [0.25 mm] | 0.005" [0.13 mm] |
| Cu to board edge – inner | 0.015" [0.38 mm] | 0.015" [0.38 mm] |
| Trace/space – ¼ oz Cu | N/A | 0.003" [0.075 mm], outer foil only |
| Trace/space – ⅜ oz Cu | N/A | 0.003" [0.075 mm], outer foil only |
| Trace/space – ½ oz Cu | 0.005" [0.13 mm] | 0.004" [0.10 mm] |
| Trace/space – 1 oz Cu | 0.007" [0.18 mm] | 0.005" [0.13 mm] |
| Trace/space – 2 oz Cu | 0.010" [0.25 mm] | 0.008" [0.20 mm] |
| Trace/space – 3 oz Cu | N/A | 0.014" [0.35 mm] |
| Solder mask | ||
| Liquid photo-imageable | Green, Blue, Red, Black, Transparent, Purple, White | |
| Direct imaging | Yes, all solder mask direct imaged | |
| Via plug (IPC-4761, Type IV) | Yes | |
| Filled (IPC-4761, Type VII) | Yes | |
| Legend | ||
| Inkjet | White | |
| Liquid photo-imageable | White, Black, Yellow | Blue, Red, Green |
| Final finish | ||
| ENIG | Yes | |
| Immersion silver | Yes | |
| Flash gold (full body) | Yes | |
| HASL (tin/lead) | Yes | |
| Hard gold | Yes | |
| Carbon paste | Yes | |
| OSP | Yes | |
| Soft gold | Yes (outsourced) | |
| ENEPIG | Yes (outsourced) | |
| DI gold | Yes (outsourced) | |
| Immersion tin | Yes (outsourced) | |
| CNC machining | ||
| Router bit diameter | 0.0945" [2.40 mm] | 0.0157" [0.40 mm] – 0.125" [3.175 mm] |
| Countersink | 82°, 90°, 100°, 110° | |
| Back drill | Yes | |
| Milling | Yes | |
| Counterbore | Yes | |
| V-score | Yes | |
| Jump score | Yes | |
| Edge bevel | Yes | Recessed |
| Edge plating | Yes | |
| Castellated edges | Min. dia. 0.020" [0.50 mm] | |
Next-generation electronics need more than standard FR4. We build with materials engineered for performance, reliability and harsh environments.
Have a material requirement that isn't listed in our capability sheets? Ask us; we'll tell you what we can build.
Ask about materialsSelect a topic to expand it.
Ideally supplied as a single design layer or as an Adobe PDF, this drawing should detail all the fabrication requirements for the part along with fully dimensioned mechanical details, including a reference drill drawing. Details not to overlook include:
You need to tell us:
* Measured over exposed conductors.
One of the design layers should include a board outline. Like circuitry artwork, board profiles should be accurately drawn, without dimensions. Dimensioned drawings should be supplied separately. All lines should be drawn with a single tool, aperture, or pen, with an assumed thickness of zero. Only the centres of drawing lines will be used as definitions for machined board edges. Each line drawn will represent an edge of the finished PCB.
Optimizing hole diameters (minimizing the number of hole sizes) within your design, and ideally within your CAD library, can help to reduce PCB fabrication cost.
Unless otherwise dictated by current handling requirements, Enigma recommends the use of ½ oz base Cu. Compared to 1 oz base Cu, ½ oz Cu provides the following benefits:
With standard processing, outer layer conductors as well as those on layers with blind or buried vias receive additional electroplated copper during the metallization of the layer-to-layer interconnects (via holes). Please refer to Enigma's prepared stack-up detail for estimated finished Cu thickness.
Arcs and circles should be represented in the CAD database and the resulting output file as true circular entities. Many CAD systems create or output arcs and circles as hundreds of short line segments, which are problematic for CAM systems. Apart from dramatically increasing the data size of a file, segmented arcs can reduce already critical feature-to-feature spacing.
When creating solder mask openings, consistency is important. If possible, avoid different solder mask annular ring clearances. We recommend that a solder mask pad be equal in size to the copper pad (except fiducials). During tooling, Enigma will increase the solder mask clearance to the required size.
If solder dams (the distance between edges of solder mask openings for adjacent pads) are required, the minimum solder dam width is 0.003". Allow at least 0.008" between the edges of adjacent copper pads to account for solder mask clearances when solder dams are required.
Note: solder dams cannot be achieved on SMT devices of ≤ 0.0157" pitch.
Note: all features within 0.005" of solder pads will be clipped away to achieve IPC specifications.
The following is required to validate controlled impedance requirements before fabrication:
The fabricator must be given the latitude to suggest adjustments to all of the above to achieve the desired nominal impedance value.
While your design might well meet your fabricator's minimum capabilities for conductor size and spacing, gains in production yield, and so a lower part cost over the life of the product, can be realized by running a clean-up pass during the design stage. The extra effort to increase the parameters where possible, by even just 1 mil, is good design practice and pays dividends in the long run.
Please contact us for clarification on any design issue.
Send us your Gerbers or ODB++ files and get a quote within 24 hours.