Manufacturing Capabilities
Advanced PCB Materials
Next-generation electronics need more than standard FR4. We build with materials engineered for performance, reliability and harsh environments.
Low-loss laminates for RF and AI systems
Low dielectric loss for high-frequency signal integrity
Stable electrical performance at mmWave frequencies and high data rates
Faster, more efficient RF and AI hardware
High-Tg materials for thermal stability
High glass transition temperature (Tg ≥ 170 °C)
Resists heat and dimensional change during assembly and operation
Improved reliability in high-temperature environments
Aluminum and cryogenic-compatible materials for quantum systems
Aluminum PCBs for thermal management and lightweight designs
Cryogenic-compatible materials that keep performing at ultra-low temperatures
Built for quantum computing and quantum sensing hardware
At Enigma: we have licensed D-Wave Systems technology to manufacture quantum PCB holders here in Burnaby. Learn more about our quantum PCBs →
Have a material requirement that isn't listed in our capability sheets? Ask us; we'll tell you what we can build.
Manufacturing Guidelines
Design tips to help your boards build faster, with better yield and lower cost. Tap a topic to expand it.
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Ideally supplied as a single design layer or as an Adobe PDF, this drawing should detail all the fabrication requirements for the part along with fully dimensioned mechanical details, including a reference drill drawing. Details not to overlook include:
Specify maximum allowable radius for inside corners (r0.050” preferred).
Specify base copper thickness for all circuit layers.
Identify holes as plated or non-plated.
Sort hole sizes in ascending order.
You need to tell us:
Board dimensions and tolerances
Finished thickness* / multi-layer stack-up detail
Dielectric specifications (if any)
Plating finish
Solder mask colour
Legend colour
Controlled impedance (if any)
* Measured over exposed conductors
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One of the design layers should include a board outline. Like circuitry artwork, board profiles should be accurately drawn, without dimensions. Dimensioned drawings should be supplied separately. All lines should be drawn with a single tool, aperture, or pen, with an assumed thickness of zero. Only the centers of drawing lines will be used as definitions for machined board edges. Each line drawn will represent an edge of the finished PCB. Things to keep in mind:
It is useful to provide a reference dimension from a non-plated hole to a board edge.
Crop marks or layer registration marks are not required on each data layer; however, care should be taken to output all layers with the same datum point.
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Optimizing hole diameters (minimizing the number of hole sizes) within your design, and ideally within your CAD library, can help to reduce PCB fabrication cost.
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Unless otherwise dictated by current handling requirements, Enigma recommends the use of ½oz base Cu. Compared to 1oz base Cu, the use of ½oz Cu provides the following benefits:
A reduction in etch loss means that it is easier to resolve the design width of traces and component lands on the finished part. This is particularly advantageous on controlled impedance designs or on designs utilizing fine pitch devices.
A reduced environmental impact.
With standard processing, outer layer conductors as well as those on layers with blind or buried vias receive additional electroplated copper during the metallization of the layer-to-layer interconnects, i.e. via holes. Please refer to Enigma’s prepared stack-up detail for estimated finished Cu thickness.
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Wherever possible, flash (negative) planes instead of drawn (copper pour) should be created, as the reduced data size improves processing time.
Drawn planes should be filled using the largest line width possible in order to produce the required fill resolution. Filling drawn planes in a single direction also reduces the size of the data set.
If hatched fill is used, orthogonal hatch (not diagonal) is preferred.
Voids in hatched planes should not be smaller than 0.015” x 0.015”.
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It is preferred that any arcs and circles created be represented in the CAD database and the resultant output file as true circular entities. Many CAD systems create and/or output arcs and circles as hundreds of short line segments, which are problematic to CAM systems. Apart from dramatically increasing the data size of a file, segmented arcs can reduce already critical feature-to-feature spacing.
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When creating solder mask openings, consistency is important. If possible, different solder mask annular ring clearances should be avoided. We recommend that a solder mask pad should be equal in size to the copper pad (except fiducial). During the tooling process, Enigma will increase the solder mask clearance to the required size.
If solder dams (distance between edges of solder mask openings for adjacent pads) are required, please note that the minimum solder dam width is 0.003”. At least 0.008” should be allowed between the edges of adjacent copper pads to account for solder mask clearances when solder dams are required.
Note: Solder dams cannot be achieved on SMT devices of <=0.0157” pitch.
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For improved clarity, use 0.005” lines for all screen-printed text and graphics.
Keep all screen print features at least 0.005” away from solder pads.
Note: All features within 0.005” from solder pads will be clipped away to achieve IPC specifications.
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To reduce rounding errors, a minimum of 4 decimal place accuracy is recommended for outputs in imperial units and 5 decimal places for metric.
Use the same output precision for Gerber and drill outputs.
Create library footprints with high precision if the software has a separate setting for the library.
All layers should be output as viewed from the top (primary) side using the same origin.
Data output should not be set to mirror any layers.
It is recommended to review all files in a standalone Gerber viewer prior to sending to a manufacturer.
ODB++ also accepted.
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The following is required to validate controlled impedance requirements prior to fabrication:
Signal layer.
Reference plane layer(s).
Impedance line width (preferably isolated on the layer by the use of a unique line width).
The desired impedance value with tolerance.
A suggested board stack-up.
The fabricator must be given the latitude to suggest adjustments to all of the above to achieve the desired nominal impedance value.
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A plating bar connecting gold fingers together is not required.
A minimum 0.030” clearance must be maintained between the edge of a gold finger or selective hard gold feature and any plated through hole feature.
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While your design might well meet your fabricator’s minimum capabilities in regards to conductor size and spacing, gains in production yield, and thus a reduction in part cost over the lifetime of the product, can be realized by running a clean-up pass during the design stage. The extra effort taken now to increase the parameters where possible by even just 1 mil is not only good design practice but will pay dividends in the long run.
Please contact us for clarification on any design issue!